The invention relates to the field of clock and data recovery circuits, and in particular, to a circuit that can be used to program the phase of the recovered clock relative to the phase of the received data using two LC resonant tanks as clock drivers, where the two LC tanks have individually adjustable center frequencies.
Many phase-locked loop (PLL) arrangements sample and retime using a recovered clock (RCLK). When the PLL is in its locked state, the falling edges of RCLK are aligned to the zero crossings in the input data. A flip-flop at the input of the phase detector samples the input on the rising edge of the RCLK to balance the setup and hold times. The quantization in this case occurs in both time and amplitude. Equal setup and hold times should provide maximum immunity to bit errors when there is jitter on the transitions of input data.
Data recovery circuits in fiber optic communication channels have benefited from the ability to move the significant instance in time within a data eye. Prior art configurations incorporating a static phase adjust feature employ an auxiliary flip-flop with a phase shifted clock relative to the clock at the phase detector. This implementation of a static phase adjust feature uses additional power for an auxiliary channel. Furthermore, bit errors made by the phase detector due to the suboptimal sampling phase can lead to incorrect phase adjustments that would increase the jitter on RCLK.